1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor package; and, more particularly, to a method of manufacturing a semiconductor package to form a rearrangement wiring layer by etching a metal layer after forming a pad unit on the metal layer with a different bonded panel including at least one metal layer and mounting a semiconductor chip electrically connected to the pad unit.
2. Description of the Related Art
A recent trend of an electronic industry is to manufacture a product which is lighter, miniaturized, high-speed, multi-functional and high-performance and has high reliability at a low cost. One of important technologies for achieving an object to deign the product is a semiconductor package.
The semiconductor package as a technology for effectively packaging a device used in an electronic product has been developed in various types because it is a technology to decide a performance of a semiconductor element and a cost, a performance and reliability of a final product.
The semiconductor package has been manufactured by a flip chip method using a bump ball technology for electrical connection between semiconductor chips or the semiconductor chip and a substrate. In the bump ball technology, there is a problem that the number of input and output pads of the package and a size of the chip are limited due to a limit in fining a bump ball. In other words, if miniaturization of the semiconductor chip or the number of the input and output pads is increasing, there is a limit to the package in that all of the bump balls as final input and output terminals can not be received in a top surface of the semiconductor chip.
In order to improve the above problem, there has been developed the package with an embedded structure for mounting the semiconductor chip inside a circuit board, a fan-out structure for positioning the bump ball as the final input and output terminal of the semiconductor chip at an outer circumferential surface of the semiconductor chip, or the like.
Herein, the package with the embedded structure or the fan-out structure is manufactured by a build-up method in which a metal layer is built up from an electric contact pattern of the semiconductor chip after mounting the semiconductor chip. However, the build-up method has problems in that a package process is complicated and a production cost is increasing since a layer stacking process, a via hole forming process for interlayer connection, or the like should be performed.
Further, in the build-up method, particularly, a cure process and a stacking process, CTE (Coefficient of Thermal Expansion) mismatch and warpage between a wafer substrate and the semiconductor chip are caused, which leads to misalignment in case that a fine pitch chip is mounted.